1. Field of the Invention
The present invention relates to a display system for displaying an image by inputting a digital video signal. Also, the present invention relates to an electronic device using the display system.
2. Description of the Related Art
A display system in which light emitting elements are arranged in respective pixels and light emission of the light emitting elements is controlled to display an image will be described below.
Here, an example in the case where a light emitting device is an element (OLED element) having a structure in which an organic compound layer for producing light emission upon generation of an electric field is sandwiched between an anode and a cathode will be described. Also, the light emitting element indicates both an element using light emission produced at transition from a singlet exciton to a ground state (fluorescence) and an element using light emission produced at transition from a triplet exciton state to the ground state (phosphorescence). As the organic compound layers, there are a hole injection layer, a hole transport layer, a light emitting layer, an electron transport layer, an electron injection layer, and the like. Basically, the light emitting element has a structure in which the anode, the light emitting layer, and the cathode are laminated in order. In addition, there are a structure in which the anode, the hole injection layer, the light emitting layer, the electron injection layer, and the cathode are laminated in this order, a structure in which the anode, the hole injection layer, the hole transport layer, the light emitting layer, the electron transport layer, the electron injection layer, and the cathode are laminated in this order, and the like.
A display system includes a display and a peripheral circuit for inputting a signal to the display. The display is composed of a source signal line driver circuit, a gate signal line driver circuit, and a pixel portion. The pixel portion has a structure in which pixels are arranged in matrix.
The display system in which thin film transistors (hereinafter referred to as TFTs) are arranged in the respective pixels and light emission of light emitting elements in the respective pixels is controlled by the TFTs to perform display (active matrix display system) will be described. A method of controlling light emission of the light emitting elements in the respective pixels in the case where two TFTs are arranged in each of the pixels will be described here.
First, a structure of the pixel will be described in detail. FIG. 21A shows a structure of the pixel portion in the display system.
Source signal lines S1 to Su, gate signal lines G1 to Gv, and power supply lines V1 to Vu are located in a pixel portion 700 to arrange pixels with u (u is a natural number) columns and v (v is a natural number) rows. Each of pixels 800 has a switching TFT 801, a driver TFT 802, a storage capacitor 803, and a light emitting element 804.
FIG. 21B is an enlarged view of one pixel in the pixel portion shown in FIG. 21A. The pixel is composed of one line S of the source signal lines S1 to Su, one line G of the gate signal lines G1 to Gv, one line V of the power supply lines V1 to Vu, the switching TFT 801, the driver TFT 802, the storage capacitor 803, and the light emitting element 804.
The gate electrode of the switching TFT 801 is connected with the gate signal line G. With respect to the source region and the drain region of the switching TFT 801, one is connected with the source signal line S and the other is connected with the gate electrode of the driver TFT 802 and one electrode of the storage capacitor 803. With respect to the source region and the drain region of the driver TFT 802, one is connected with the power supply line V and the other is connected with the anode or the cathode of the light emitting element 804. Of two electrodes of the storage capacitor 803, one electrode which is not connected with the driver TFT 802 and the switching TFT 801 is connected with the power supply line V.
Here, when the source region or the drain region of the driver TFT 802 is connected with the anode of the light emitting element 804, the anode of the light emitting element 804 is called a pixel electrode and the cathode thereof is called a counter electrode. On the other hand, when the source region or the drain region of the driver TFT 802 is connected with the cathode of the light emitting element 804, the cathode of the light emitting element 804 is called a pixel electrode and the anode thereof is called a counter electrode. Also, a potential provided for the power supply line V is called a power source potential and a potential provided for the counter electrode is called a counter potential.
Here, the counter potential can be changed by an external power source (not shown) such that this potential becomes a potential of the same order as the potential of the power supply lines V1 to Vu (power source voltage) or has a potential difference between the potential of the power supply lines V1 to Vu, to the extent that the light emitting device 804 can emit light.
The switching TFT 801 and the driver TFT 802 each may be a p-channel TFT or an n-channel TFT. However, when the pixel electrode of the light emitting element 804 is the anode, the driver TFT 802 is desirably a p-channel TFT and the switching TFT 801 is desirably an n-channel TFT. On the other hand, when the pixel electrode is the cathode, the driver TFT 802 is desirably an n-channel TFT and the switching TFT 801 is desirably a p-channel TFT. Because it is desirable that a TFT is operated with a state that a potential of the source region is fixed.
Note that the storage capacitor 803 is not necessarily provided. For example, the case where an n-channel TFT used as the driver TFT 802 has an LDD region provided so as to overlap a gate electrode through a gate insulating film is noted. A parasitic capacitor which is generally called a gate capacitor is produced in the overlapped region. The parasitic capacitor can be actively used as a storage capacitor for keeping a voltage applied to the gate electrode of the driver TFT 802.
Next, a circuit for inputting signals to the source signal line driver circuit and the gate signal line driver circuit in the display will be described. FIG. 17 is used for the description. Note that a signal inputted to the display system is called a digital video signal. An example of a display system for representing a gradation by inputting a digital video signal of n bits will be described here.
A digital video signal is read into a signal control circuit 1101 and a digital image signal (VD) is outputted to a display 1100. Here, a signal to be inputted to the display, which is converted by editing the digital video signal (first image signal) in the signal control circuit is called the digital image signal (second image signal).
Signals for driving a source signal line driver circuit 1107 and a gate signal line driver circuit 1108 in the display 1100 are inputted from a display controller 1102. Also, the source signal line driver circuit 1107 includes a shift register 1110, an LAT(A) 1111, and an LAT(B) 1112. Although not shown, a level shifter, a buffer, and the like may be further provided.
The signal control circuit 1101 and the display controller 1102 will be described.
First, a structure and an operation of the signal control circuit 1101 will be described. The signal control circuit 1101 is composed of a CPU 1104, a memory-A 1105, a memory-B 1116, and a memory controller 1103.
A digital video signal inputted to the signal control circuit 1101 is inputted to the memory-A 1105 through the CPU 1104. Here, the memory-A 1105 and the memory-B 1106 each have a capacity capable of storing a digital video signal of n-bits corresponding to all pixels of a pixel portion 1109 in the display 1100. When a signal corresponding to one frame period is stored in the memory-A 1105, the signals of the respective bits are read out in order by the memory controller 1103 and are inputted as the digital image signals (VD) to the source signal line driver circuit 1107. The digital video signal is sampled alternately using the memory-A 1105 and the memory-B 1106.
Hereinafter, both the memory-A and the memory-B in the above-mentioned signal control circuit are integrally indicated as a memory. The memory is composed of a plurality of memory elements arranged in matrix. The memory elements are selected by an address of (x, y).
The memory controller 1103 for controlling input and output of the digital video signal will be described using FIG. 19. The memory controller 1103 is composed of a memory read/write control (hereinafter referred to as a memory R/W) circuit 1202, a standard oscillating circuit 1203, a variable dividing circuit 1204, an x-counter 1205a, a y-counter 1205b, an x-decoder 1206a, and a y-decoder 1206b. 
The memory controller 1103 selects an address (x, y) of the memory in accordance with signals from the CPU 1104. Also, a memory R/W signal for selecting an operation for writing a signal into the memory or an operation for reading out a signal from the memory is outputted.
Next, signals such as the start pulses and the clock pulses are outputted to the source signal line driver circuit and the gate signal line driver circuit. The display controller 1102 will be described using FIG. 20. The display controller 1102 is composed of a standard clock generating circuit 1301, a horizontal clock generating circuit 1303, a vertical clock generating circuit 1304, and a power source control circuit 1305 for a light emitting element.
A clock signal 31, a horizontal periodic signal 32, and a vertical periodic signal 33 are inputted from the CPU 1104 to the display controller 1102. Thus, the display controller 1102 outputs a clock pulse S_CLK and a start pulse S_SP for the source signal line driver circuit. Also, the display controller 1102 outputs a clock pulse G_CLK and a start pulse G_SP for the gate signal line driver circuit. The power source control circuit 1305 for the light emitting element controls a potential of a counter electrode (counter potential) of a light emitting element in each pixel of the display.
Turning again to FIG. 17, the start pulse S_SP and the clock pulse S_CLK for the source signal line driver circuit, which are outputted from the display controller 1102, are inputted to the shift register 1110 of the source signal line driver circuit 1107 of the display 1100. The start pulse G_SP and the clock pulse G_CLK for the gate signal line driver circuit, which are outputted from the display controller 1102, are inputted to the gate signal line driver circuit 1108 of the display 1100.
Here, generally, the respective driver circuits (source signal line driver circuit and gate signal line driver circuit) composing the display are formed on another substrate such as a single crystalline IC substrate and the resultant substrate is bonded onto a substrate on which pixels are formed (pixel substrate) to incorporate them into a display system. There is TAB (tape automated bonding) or the like as the bonding method. However, as described above, when the driver circuits are incorporated into the display system, an increase in a wiring resistance of the connection portion, poor connection thereof, an increase of an area of a peripheral portion (frame region) of a pixel portion, and the like become problems.
Thus, a method of forming the driver circuits on the pixel substrate by using TFTs is proposed.
Generally, a TFT using an amorphous semiconductor thin film (hereinafter referred to as an a-TFT) is used as a TFT composing a pixel in an active matrix display system. Here, in the case of the a-TFT, there is a problem such as small field effect mobility. Thus, in the case of driver circuits using the a-TFT, there is a problem that a frequency characteristic cannot be improved. Therefore, a display system having a structure in which a TFT using a polycrystalline semiconductor thin film (hereinafter referred to as a p-TFT) is formed as a TFT composing a pixel portion and driver circuits is proposed. The p-TFT has larger field effect mobility than the a-TFT. Thus, a display system in which the pixel portion and the respective driver circuits are formed on the same substrate (hereinafter referred to as a display substrate) is proposed.
According to a conventional display system, a memory, a memory controller, a display controller, and the like (hereinafter the memory controller, the display controller, and the like are referred to as control circuits) which compose the display system are formed on another substrate such as a single crystalline IC substrate and connected onto a display substrate in which pixels and driver circuits are formed. Thus, when connecting the memory and the control circuits onto the display substrate, a wiring capacitance in the connection portion becomes a problem. Since wiring capacitances in the connection portions between the respective driver circuits and the pixel portion which are formed on the display substrate, and the memory and the control circuits which are externally attached thereto, are increased, the power consumption of the entire display system cannot be reduced.